1. Field of the Invention
The present invention relates to a solid state imaging apparatus with a horizontal charge transfer gate which can transfer signal charge faster.
2. Description of the Related Art
In a conventional solid state imaging apparatus, there are an individual mode in which a signal charge of each of pixels is individually outputted and an interline mode in which signal charges for a plurality of pixels adjacent to each other are collectively outputted. When the signal charges of the plurality of pixels are added and outputted, a resolution is degraded. However, it is possible to shorten a time required to output all the signal charges to thereby increase a frame rate. Both of the above-mentioned operations are necessary, when there are a case where it is desired to obtain a fine reproduction image and a case where it is desired to obtain a reproduction image having a high frame rate in the same image system. Especially in a solid state imaging apparatus having a large number of pixels in which it takes a long time to output the signal charges of all the pixels. As a result, the frame rate is decreased so that the motion of an object in a reproduction image becomes unnatural, when the motion of the object is large. Thus, when the object moves, the frame rate is desired to be higher in order to obtain a reproduction image in which the motion is natural.
As an example, a case will be described below where signal charges for four pixels of two pixels in a horizontal direction and two pixels in a vertical direction are added and outputted in a solid state imaging apparatus.
In order to add signal charges of two pixels adjacent to each other in the vertical direction, the signal charge in a vertical charge transfer register are transferred two times within a horizontal blanking period. A horizontal charge transfer register receives the signal charges corresponding to two rows from each of the vertical charge transfer registers and sequentially transfers them to an output section. The signal charges corresponding to the two pixels adjacent to each other in the vertical direction are added. Thus, the number of times of the horizontal transfer required to output the signal charges of all the pixels is half that of the case where the signal charges are individually outputted. Hence, a time required to output the signal charges of all the pixels is also half.
FIG. 1 is a sectional side view showing a wiring connection and a structure of a side section along a transfer direction of the horizontal charge transfer register 405 in the solid state imaging apparatus 400. Referring to FIG. 1, signal charges of two pixels adjacent to each other in the horizontal direction are added. At this time, the timings of a pulse xcfx86H1L applied to a final electrode of the horizontal charge transfer register 405 and a reset pulse xcfx86R applied to a reset gate electrode are set to have the periods equal to two times of those of the drive pulses xcfx86H1 and xcfx86H2 applied to the transfer electrode of the horizontal charge transfer register 405. Such a method is disclosed in, for example, Japanese Laid Open Patent Application (JP-A-Heisei 4-256364).
The horizontal charge transfer register 405 is a CCD (Charge Coupled Device). As shown in FIG. 1, a P-type diffusion layer 702 serving as a charge transfer region of the horizontal charge transfer register 405 is formed on a main surface of an N-type diffusion layer 701. P+-type regions 703 serving as barrier sections of the charge transfer region are formed in the P-type diffusion layer 702 at the same interval along a charge transfer direction. Also, charge transfer electrodes 705 are arrayed through an insulating layer 704 on the surface of the P-type diffusion layer 702.
Each charge transfer electrode 705 is composed of a set of an accumulation section electrode 705A above the P-type diffusion layer 702 and a barrier section electrode 705B above the P+-type region 703. The charge transfer electrodes 705 are alternatively connected to one of two horizontal bus lines 706. Two-phase drive pulses xcfx86H1 and xcfx86H2 are applied through the horizontal bus lines 706 to the respective transfer electrodes 705. The drive pulses xcfx86H1 and xcfx86H2 have a phase difference of 180 degrees from each other.
A final electrode 707, an output gate electrode 708 and a reset gate electrode 709 are formed on the insulating layer 704 in this order toward the end of the horizontal charge transfer register 405. A pulse xcfx86H1L, a direct current voltage OG and a reset pulse xcfx86R are applied to the above electrodes, respectively.
A first N+-type diffusion layer 710 is formed in the P-type diffusion layer 702 between the output gate electrode 708 and the reset gate electrode 709 to serve as an electrode of a floating capacitor for a charge detector 407. A second N+-type diffusion layer 711 is formed on a side opposite to the first N+-type diffusion layer 710 with respect to the reset gate electrode 709 to serve as a reset gain. The first N+-type diffusion layer 710 is connected to an input terminal of the charge detector 407. On the contrary, the second N+-type diffusion layer 711 is fixed to a predetermined direct current potential VRD.
FIGS. 2A to 2D are timing charts showing the pulse signals xcfx86H1 , xcfx86H2, xcfx86H1L and xcfx86R applied to the transfer electrodes, the final electrode and the reset gate electrode of the horizontal charge transfer register 405. The timing charts show the pulse signals when the signal charges of the respective pixels are individually outputted. the drive pulse signals xcfx86H1 and xcfx86H2 are two-phase two-value pulse signals which are out of phase by 180 degrees from each other. The pulse signal xcfx86H1L has the same phase as the drive pulse signal xcfx86H1. In FIGS. 2A to 2D, a level HL indicates a low level of the drive pulse signals xcfx86H1 and xcfx86H2 and the pulse signal xcfx86H1L, and a level HH indicates a high level of the drive pulse signals xcfx86H1 and xcfx86H2 and the pulse signal xcfx86H1L. Also, levels RH and RL indicate the high level and low level of the reset pulse signal xcfx86R.
FIGS. 3A to 3D are diagram showing the accumulation states of the signal charges and the potentials along the transfer direction of the horizontal charge transfer register 405 at the respective times t1 to t3 of FIGS. 2A to 2D. FIG. 3A schematically shows the horizontal charge transfer register 405. FIGS. 3A to 3D show the states of the signal charge CS and potential distributions at the respective portions of the horizontal charge transfer register 405, for each of the times t1 to t3.
The signal charges CS are individually transferred through the charge transfer registers 705 to the first N+-type diffusion layer 710 serving as the electrode of floating capacitance. Thus, the voltage conversion is performed to the signal charges SC. Then, the voltage is outputted from the output terminal 408 through the charge detector 407 of the solid state imaging apparatus to an external unit. After that, the signal charges of the first N+-type diffusion layer 710 are sent out to the second N+-type diffusion layer 711 serving as the reset drain, when the pulse signal xcfx86R is applied to the reset gate electrode 709.
A case of adding and outputting signal charges of two pixels adjacent to each other in a horizontal direction will be described below. FIGS. 4A to 4D are timing charts showing the pulse signals applied to the transfer electrode, the final electrode and the reset gate electrode of the horizontal charge transfer register 405. FIGS. 5A to 5E are diagrams showing the accumulation states of the signal charges and the potentials along the transfer direction of the horizontal charge transfer register 405 at the respective times t1 to t4 of FIGS. 4A to 4D. Also, FIGS. 5A to 5E correspond to FIGS. 3A to 3D.
As shown in FIGS. 4A to 4D, periods of the drive pulse signals xcfx86H1 and xcfx86H2 applied to the transfer electrodes of the horizontal charge transfer register 405 are equal to a period when a signal charge of one pixel is individually outputted. However, the period of the pulse signal xcfx86H1L applied to the final electrode 707 and the period of the pulse signal xcfx86R applied to the reset gate electrode 709 are set to be equal to two times that of the case of individually outputting the signal charges, as seen from FIGS. 2C and 2D. Accordingly, the signal charge CS are transferred through the horizontal charge transfer register 405 to the first N+-type diffusion layer 710, after the signal charges CS corresponding to the two pixels adjacent to each other are added below the final electrode 707.
However, the frame rate is not changed, even if the signal charges of the pixels adjacent to each other in the horizontal direction are added and outputted, differently from the case of adding and outputting the signal charges of the pixels adjacent to each other in the vertical direction. That is, the drive pulse signals xcfx86H1 and xcfx86H2 applied to the transfer electrodes 705 of the horizontal charge transfer register 405 are the same as those of the case of individually outputting the signal charges CS of the respective pixels. Thus, a rate at which the signal charge is transferred in the horizontal charge transfer register 405 is not changed. As a result, a time required to output all the signal charges of the horizontal charge transfer register 405 is also same. Hence, even if the signal charge corresponding to a total of four pixels of two pixels in the horizontal direction and two pixels in the vertical direction is added and outputted, the frame rate can be increased only to two times, although a data amount is xc2xc.
In conjunction with the above description, a driving method in a solid state imaging apparatus is disclosed in Japanese Laid Open Patent Application (JP-A-Heisei 4-262679). In this reference, the charge read out in response to a TG pulse is transferred for one stage in response to a line shift pulse A in a first field. The charge transferred into a horizontal CCD register is transferred through the horizontal CCD register. Thereafter, the charge in a vertical CCD register is transferred for two stages in response to a line shift pulse B during one horizontal blanking period. By transfer for the two stage, the charges for two photodiodes adjacent in the vertical CCD register are added to produce an addition charge. The addition charge is transferred in a horizontal direction. In a second field, the vertical transfer is carried out twice in response to the line shift pulse B during one horizontal blanking period and the charges from the two adjacent photodiodes are added in the horizontal CCD register. The added charges are transferred in the horizontal direction.
Also, a solid state imaging apparatus is disclosed in Japanese Laid Open Patent Application (JP-A-Heisei 4-277986). In this reference, a shift register is composed of unit circuits connected in series and the unit circuit is composed of 2-stage clocked inverter. The shift register is divided into three blocks A, B and C to which start pulses xcfx86STA, xcfx86STB and xcfx86STC are applied, respectively. Also, clock pulses xcfx861, /xcfx861, xcfx862 and /xcfx862 are supplied in common. By controlling the start pulses and the clock pulses supplied to the blocks A, B and C, the outputs of the blocks A, B and C are changed to scan a part or whole of pixels.
Also, an image recording apparatus is disclosed in Japanese Laid Open Patent Application (JP-A-Heisei 5-30437). In this reference, an imaging plane 15 of a solid state imaging apparatus in which photoelectric converting elements are arranged in a matrix is divided into blocks B1, B2, . . . , B16 in a column direction. The column of the photoelectric converting elements is a scanning line. The scanning lines of the blocks are scanned to produce a multi-channel video signals S1, S2, . . . , S16. A first scanning circuit 16 provides line scanning start point H1, H2, . . . , H16 in the blocks B1, B2, . . . , B16 in a scanning line direction, and selects read blocks. A second scanning circuit 17 carries out the selection of the line scanning start point H1, H2, . . . , H16 and the number of line scanning pixels. Imaging areas having different the line scanning start positions are selected in response to drive signals using the first and second scanning circuits to produce a multi-channel video signal.
Also, an imaging sensor is disclosed in Japanese Laid Open Patent Application (JP-A-Heisei 10-136244). In this reference, an interline type CCD image sensor has a color filter suitable for read of all pixels in a sequential line scan. The CCD imaging sensor is driven a high speed mode in a normal mode, and in a high precision mode only when a trigger is pushed. The imaging sensor outputs one line signal for every three lines in a vertical direction in the high speed mode. An image is displayed on a LCD display section at a frame rate of 60 frames/sec. in the high speed mode.
Also, a solid state imaging apparatus is disclosed in Japanese Laid Open Patent Application (JP-A-Heisei 10-107252). In this reference, the imaging apparatus is composed vertical transfer sections 12 for transferring charges generated in a light receiving section in a vertical direction and a horizontal transfer section 4 for transferring the charges supplied from the vertical transfer sections 12 in a horizontal direction. Charge abandon sections are provided to selectively abandon the charges from the vertical transfer sections 12 in response to a control signal xcfx86C. The charge abandon section is composed of a control electrode 34 applied with the control signal xcfx86C, a potential barrier region in which the magnitude of a barrier potential is changed in accordance with the control signal xcfx86C, and an impurity region 26 in which the charge is abandoned through the potential barrier region.
Therefore, an object of the present invention is to provide a solid state imaging apparatus with a horizontal charge transfer register which can improve a frame rate, even if signal charges of a plurality of pixels adjacent to each other in a horizontal direction are added and outputted.
In order to achieve an aspect of the present invention, a charge transfer structure includes an insulating film on a first semiconductor region, a plurality of transfer electrodes and a signal generating circuit. The plurality of transfer electrodes are formed on the insulating film, and each of the plurality of transfer electrodes is composed of a barrier electrode and an accumulation electrode. The signal generating circuit generates first to 2N-th (N is a positive integer more than 1) pulse signals which are supplied to every 2N transfer electrodes of the plurality of transfer electrodes in an interline mode, such that a signal charge can be transferred for the 2N transfer electrodes at maximum during one cycle of the first to 2N-th pulse signals.
Here, the charge transfer structure may further include a second semiconductor region formed in a surface portion of the first semiconductor region below the barrier electrode of each of the plurality of transfer electrodes, the second semiconductor region having a same conductive type as the first semiconductor region.
Also, every adjacent two of the first to 2N-th pulse signals may have a same phase, and odd order pulse signals of the first to 2N-th pulse signals may have different phases. In this case, a different offset voltage is applied to every adjacent two of the first to 2N-th pulse signals.
Also, when N is 2, the first pulse signal and the second pulse signal have a same phase, the third pulse signal and the fourth pulse signal have a same phase, and the first pulse signal and the third pulse signal are opposite in phase. In this case, offset voltages are applied to the first and third pulse signals. Also, a lower level of the first pulse signal is higher than a higher level of the second pulse signal, and a lower level of the third pulse signal is higher than a higher level of the fourth pulse signal.
In addition, when N is 2, the signal charge is transferred for the three electrodes during a first half of the one cycle and for the five electrodes during a second half of the one cycle, in the interline mode.
The charge transfer structure may further include an output electrode formed on the insulating film to detect an accumulated charge, and an output semiconductor region formed in a surface portion of the first semiconductor region below the output electrode to accumulate as the accumulated charge the signal charges transferred using the plurality of transfer electrodes. Also, the charge transfer structure may further include a reset electrode formed on the insulating film close to the output electrode and operating to abandon the accumulated charge from the output semiconductor region in response to a reset signal generated by the signal generating circuit.
Also, the signal generating circuit generates the first to 2N-th pulse signals in an individual mode such that all of odd order pulse signals of the first to 2N-th pulse signal have a same phase, all of even order pulse signals of the first to 2N-th pulse signals have a same phase, the first pulse signal and the second pulse signal are opposite in phase, all of the first to 2N-th pulse signals have a same higher level and a same lower level.
Also, when N is 2, the signal generating circuit generates the first to fourth pulse signals in an individual mode such that the first and third pulse signals have a same phase, the second pulse signal and the fourth pulse signal have a same phase, the first pulse signal and the second pulse signal are opposite in phase, all of the first to fourth pulse signals have a same higher level and a same lower level.
In order to achieve another aspect of the present invention, a solid state imaging apparatus includes vertical charge transfer registers, an insulating film, a plurality of transfer electrodes and a signal generating circuit. The vertical charge transfer registers transfers signal charges in a vertical direction. The insulating film is formed on a first semiconductor region. The plurality of transfer electrodes are formed on the insulating film. Each of the plurality of transfer electrodes is composed of a barrier electrode and an accumulation electrode, and the accumulation electrodes receive the signal charges from the vertical charge transfer registers. The signal generating circuit generates first to 2N-th (N is a positive integer more than 1) pulse signals which are supplied to every 2N transfer electrodes of the plurality of transfer electrodes in an interline mode, such that the signal charge can be transferred in a horizontal direction for the 2N transfer electrodes at maximum during one cycle of the first to 2N-th pulse signals.